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Replace graph with operator in Scaladoc/Javadoc

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This commit is contained in:
Richard S. Imaoka 2018-06-09 17:42:56 +09:00
parent 57615f1e88
commit 60eee84345
64 changed files with 394 additions and 394 deletions
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30
akka-stream-tests/src/test/scala/akka/stream/impl/fusing/GraphInterpreterSpecKit.scala
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@ -17,27 +17,27 @@ import scala.collection.{ Map ⇒ SMap }
object GraphInterpreterSpecKit {
/**
* Create logics and enumerate stages and ports
* Create logics and enumerate operators and ports
*
* @param stages Stages to "materialize" into graph stage logic instances
* @param upstreams Upstream boundary logics that are already instances of graph stage logic and should be
* part of the graph, is placed before the rest of the stages
* @param downstreams Downstream boundary logics, is placed after the other stages
* @param attributes Optional set of attributes to pass to the stages when creating the logics
* @param operators Operators to "materialize" into operator logic instances
* @param upstreams Upstream boundary logics that are already instances of operator logic and should be
* part of the graph, is placed before the rest of the operators
* @param downstreams Downstream boundary logics, is placed after the other operators
* @param attributes Optional set of attributes to pass to the operators when creating the logics
* @return Created logics and the maps of all inlets respective outlets to those logics
*/
private[stream] def createLogics(
stages: Array[GraphStageWithMaterializedValue[_ <: Shape, _]],
operators: Array[GraphStageWithMaterializedValue[_ <: Shape, _]],
upstreams: Array[UpstreamBoundaryStageLogic[_]],
downstreams: Array[DownstreamBoundaryStageLogic[_]],
attributes: Array[Attributes] = Array.empty): (Array[GraphStageLogic], SMap[Inlet[_], GraphStageLogic], SMap[Outlet[_], GraphStageLogic]) = {
if (attributes.nonEmpty && attributes.length != stages.length)
if (attributes.nonEmpty && attributes.length != operators.length)
throw new IllegalArgumentException("Attributes must be either empty or one per stage")
var inOwners = SMap.empty[Inlet[_], GraphStageLogic]
var outOwners = SMap.empty[Outlet[_], GraphStageLogic]
val logics = new Array[GraphStageLogic](upstreams.length + stages.length + downstreams.length)
val logics = new Array[GraphStageLogic](upstreams.length + operators.length + downstreams.length)
var idx = 0
while (idx < upstreams.length) {
@ -50,8 +50,8 @@ object GraphInterpreterSpecKit {
}
var stageIdx = 0
while (stageIdx < stages.length) {
val stage = stages(stageIdx)
while (stageIdx < operators.length) {
val stage = operators(stageIdx)
setPortIds(stage.shape)
val stageAttributes =
@ -215,7 +215,7 @@ trait GraphInterpreterSpecKit extends StreamSpec {
override def toString = "Downstream"
}
class AssemblyBuilder(stages: Seq[GraphStageWithMaterializedValue[_ <: Shape, _]]) {
class AssemblyBuilder(operators: Seq[GraphStageWithMaterializedValue[_ <: Shape, _]]) {
private var upstreams = Vector.empty[UpstreamBoundaryStageLogic[_]]
private var downstreams = Vector.empty[DownstreamBoundaryStageLogic[_]]
private var connectedPorts = Vector.empty[(Outlet[_], Inlet[_])]
@ -238,7 +238,7 @@ trait GraphInterpreterSpecKit extends StreamSpec {
}
def init(): Unit = {
val (logics, inOwners, outOwners) = createLogics(stages.toArray, upstreams.toArray, downstreams.toArray)
val (logics, inOwners, outOwners) = createLogics(operators.toArray, upstreams.toArray, downstreams.toArray)
val conns = createConnections(logics, connectedPorts, inOwners, outOwners)
manualInit(logics.toArray, conns)
@ -257,8 +257,8 @@ trait GraphInterpreterSpecKit extends StreamSpec {
_interpreter.init(null)
}
def builder(stages: GraphStageWithMaterializedValue[_ <: Shape, _]*): AssemblyBuilder =
new AssemblyBuilder(stages.toVector)
def builder(operators: GraphStageWithMaterializedValue[_ <: Shape, _]*): AssemblyBuilder =
new AssemblyBuilder(operators.toVector)
}