fix ReverseArrowSpec, #22463
This commit is contained in:
Patrik Nordwall
parent
9a5c2fa5de
commit
5848485f3c
2 changed files with 25 additions and 48 deletions
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@ -161,7 +161,7 @@ class ReverseArrowSpec extends StreamSpec {
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val src = b.add(source)
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src ~> f
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sink2 <~ f
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(the[IllegalArgumentException] thrownBy (s <~ f <~ src)).getMessage should include("already connected")
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(the[UnsupportedOperationException] thrownBy (s <~ f <~ src)).getMessage should include("Cannot wire ports in a completed builder")
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ClosedShape
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}).run(), 1.second) should ===(Seq(1, 2, 3))
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}
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@ -169,16 +169,14 @@ object TraversalBuilder {
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traversalSoFar = MaterializeAtomic(module, Array.ofDim[Int](module.shape.outlets.size)),
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inSlots = module.shape.inlets.size,
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inToOffset = module.shape.inlets.map(in ⇒ in → in.id).toMap,
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attributes
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)
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attributes)
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b
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} else {
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AtomicTraversalBuilder(
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module,
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Array.ofDim[Int](module.shape.outlets.size),
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module.shape.outlets.size,
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attributes
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)
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attributes)
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}
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}
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@ -352,8 +350,7 @@ final case class CompletedTraversalBuilder(
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traversalSoFar: Traversal,
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inSlots: Int,
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inToOffset: Map[InPort, Int],
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attributes: Attributes
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) extends TraversalBuilder {
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attributes: Attributes) extends TraversalBuilder {
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override def add[A, B, C](submodule: TraversalBuilder, shape: Shape, combineMat: (A, B) ⇒ C): TraversalBuilder = {
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val key = new BuilderKey
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@ -362,8 +359,7 @@ final case class CompletedTraversalBuilder(
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inSlots = inSlots,
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inOffsets = inToOffset,
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pendingBuilders = Map(key → this),
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attributes = attributes
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).add(submodule, shape, combineMat)
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attributes = attributes).add(submodule, shape, combineMat)
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}
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override def traversal: Traversal =
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@ -378,7 +374,7 @@ final case class CompletedTraversalBuilder(
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override def isTraversalComplete: Boolean = true
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override def wire(out: OutPort, in: InPort): TraversalBuilder =
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throw new UnsupportedOperationException("Cannot wire ports in a completed builder.")
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throw new UnsupportedOperationException(s"Cannot wire ports in a completed builder. ${out.mappedTo} ~> ${in.mappedTo}")
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override def setAttributes(attributes: Attributes): TraversalBuilder =
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copy(attributes = attributes)
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@ -406,8 +402,7 @@ final case class AtomicTraversalBuilder(
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module: AtomicModule[Shape, Any],
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outToSlot: Array[Int],
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unwiredOuts: Int,
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attributes: Attributes
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) extends TraversalBuilder {
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attributes: Attributes) extends TraversalBuilder {
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override def add[A, B, C](submodule: TraversalBuilder, shape: Shape, combineMat: (A, B) ⇒ C): TraversalBuilder = {
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// TODO: Use automatically a linear builder if applicable
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@ -445,8 +440,7 @@ final case class AtomicTraversalBuilder(
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inSlots = inSlots,
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// TODO Optimize Map creation
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inToOffset = module.shape.inlets.iterator.map(in ⇒ in → in.id).toMap,
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attributes = attributes
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)
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attributes = attributes)
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} else copy(outToSlot = newOutToSlot, unwiredOuts = newUnwiredOuts)
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}
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@ -490,8 +484,7 @@ object LinearTraversalBuilder {
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if (inPortOpt.isDefined) 1 else 0,
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traversalSoFar = MaterializeAtomic(module, wiring),
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pendingBuilder = None,
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attributes
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)
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attributes)
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}
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def addMatCompose[A, B](t: Traversal, matCompose: (A, B) ⇒ Any): Traversal = {
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@ -506,8 +499,7 @@ object LinearTraversalBuilder {
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def fromBuilder[A, B](
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traversalBuilder: TraversalBuilder,
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shape: Shape,
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combine: (A, B) ⇒ Any = Keep.right[A, B]
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): LinearTraversalBuilder = {
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combine: (A, B) ⇒ Any = Keep.right[A, B]): LinearTraversalBuilder = {
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traversalBuilder match {
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case linear: LinearTraversalBuilder ⇒
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if (combine eq Keep.right) linear
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@ -527,8 +519,7 @@ object LinearTraversalBuilder {
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inSlots = completed.inSlots,
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completed.traversal.concat(addMatCompose(PushNotUsed, combine)),
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pendingBuilder = None,
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Attributes.none
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)
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Attributes.none)
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case composite ⇒
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val inOpt = shape.inlets.headOption
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@ -546,8 +537,7 @@ object LinearTraversalBuilder {
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addMatCompose(PushNotUsed, combine),
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pendingBuilder = Some(composite),
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Attributes.none,
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beforeBuilder = if (inOpt.isDefined) PushAttributes(composite.attributes) else EmptyTraversal
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)
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beforeBuilder = if (inOpt.isDefined) PushAttributes(composite.attributes) else EmptyTraversal)
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}
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}
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@ -569,8 +559,7 @@ final case class LinearTraversalBuilder(
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traversalSoFar: Traversal,
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pendingBuilder: Option[TraversalBuilder],
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attributes: Attributes,
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beforeBuilder: Traversal = EmptyTraversal
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) extends TraversalBuilder {
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beforeBuilder: Traversal = EmptyTraversal) extends TraversalBuilder {
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protected def isEmpty: Boolean = inSlots == 0 && outPort.isEmpty
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@ -622,8 +611,7 @@ final case class LinearTraversalBuilder(
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.assign(out, inOffset - composite.offsetOfModule(out))
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.traversal
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.concat(traversalSoFar),
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pendingBuilder = None
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)
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pendingBuilder = None)
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case None ⇒
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copy(inPort = None, outPort = None, traversalSoFar = rewireLastOutTo(traversalSoFar, inOffset))
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}
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@ -661,8 +649,7 @@ final case class LinearTraversalBuilder(
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.assign(out, relativeSlot)
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.traversal
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.concat(traversalSoFar),
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pendingBuilder = None
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)
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pendingBuilder = None)
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case None ⇒
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copy(outPort = None, traversalSoFar = rewireLastOutTo(traversalSoFar, relativeSlot))
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}
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@ -686,12 +673,10 @@ final case class LinearTraversalBuilder(
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if (toAppend.isEmpty) {
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copy(
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traversalSoFar = PushNotUsed.concat(LinearTraversalBuilder.addMatCompose(traversalSoFar, matCompose))
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)
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traversalSoFar = PushNotUsed.concat(LinearTraversalBuilder.addMatCompose(traversalSoFar, matCompose)))
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} else if (this.isEmpty) {
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toAppend.copy(
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traversalSoFar = toAppend.traversalSoFar.concat(LinearTraversalBuilder.addMatCompose(traversal, matCompose))
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)
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traversalSoFar = toAppend.traversalSoFar.concat(LinearTraversalBuilder.addMatCompose(traversal, matCompose)))
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} else {
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if (outPort.nonEmpty) {
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require(toAppend.inPort.isDefined, "Appended linear module must have an unwired input port " +
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@ -704,8 +689,7 @@ final case class LinearTraversalBuilder(
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composite
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.assign(out, -composite.offsetOfModule(out) - toAppend.inSlots + toAppend.inOffset)
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.traversal
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.concat(traversalSoFar)
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)
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.concat(traversalSoFar))
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case None ⇒
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// No need to rewire if input port is at the expected position
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if (toAppend.inOffset == (toAppend.inSlots - 1))
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@ -734,8 +718,7 @@ final case class LinearTraversalBuilder(
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traversalSoFar = newTraversal,
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pendingBuilder = toAppend.pendingBuilder,
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attributes = Attributes.none,
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beforeBuilder = if (toAppend.pendingBuilder.isEmpty) EmptyTraversal else PushAttributes(toAppend.attributes)
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)
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beforeBuilder = if (toAppend.pendingBuilder.isEmpty) EmptyTraversal else PushAttributes(toAppend.attributes))
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} else throw new Exception("should this happen?")
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}
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@ -797,8 +780,7 @@ final case class CompositeTraversalBuilder(
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outOwners: Map[OutPort, BuilderKey] = Map.empty,
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unwiredOuts: Int = 0,
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attributes: Attributes,
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islandTag: IslandTag = null
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) extends TraversalBuilder {
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islandTag: IslandTag = null) extends TraversalBuilder {
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override def toString: String =
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s"""
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@ -849,8 +831,7 @@ final case class CompositeTraversalBuilder(
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traversalSoFar = finalTraversal,
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inSlots,
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inOffsets,
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attributes
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)
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attributes)
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} else this
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}
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@ -876,15 +857,13 @@ final case class CompositeTraversalBuilder(
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// TODO Optimize Map access
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pendingBuilders = pendingBuilders.updated(builderKey, result),
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// pendingBuilders = pendingBuilders - builderKey,
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unwiredOuts = unwiredOuts - 1
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)
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unwiredOuts = unwiredOuts - 1)
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} else {
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// Update structures with result
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copy(
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inBaseOffsetForOut = inBaseOffsetForOut - out,
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unwiredOuts = unwiredOuts - 1,
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pendingBuilders = pendingBuilders.updated(builderKey, result)
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)
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pendingBuilders = pendingBuilders.updated(builderKey, result))
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}
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// If we have no more unconnected outputs, we can finally build the Traversal and shed most of the auxiliary data.
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@ -934,8 +913,7 @@ final case class CompositeTraversalBuilder(
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reverseBuildSteps = newBuildSteps,
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inSlots = inSlots + submodule.inSlots,
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pendingBuilders = pendingBuilders.updated(builderKey, submodule),
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inOffsets = newInOffsets
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)
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inOffsets = newInOffsets)
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} else {
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// Added module have unwired outputs.
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@ -969,8 +947,7 @@ final case class CompositeTraversalBuilder(
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inBaseOffsetForOut = newBaseOffsetsForOut,
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outOwners = newOutOwners,
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pendingBuilders = pendingBuilders.updated(builderKey, submodule),
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unwiredOuts = unwiredOuts + submodule.unwiredOuts
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)
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unwiredOuts = unwiredOuts + submodule.unwiredOuts)
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}
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added.completeIfPossible
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